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Altera_Forum
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14 years ago

delay line

Hello, i'm not expert about fpga so i'd like to read some hints from more expert users.

I need to create a delay line on cyclone II, i will use it to implement a flash tapped delay line based time to digital converter. i need a resolution (lsb) around 100 ps, the resolution of this kind of tdc it's bounded by the propagation delay of the delay element. What should i use to make such a delay line?

i read somewhere that the carry chain of the logic cell in arithmetic mode has a propagation delay cin cout of 70 ps (i wonder where i find this info on the datasheet), so i tried to exploit the carry chain using the add_sub megafunction but the place and route tool didn't put it on LEs in arithmetic mode but in logic mode, so i'd like to know if there's a way to force the place and route to configure the logic cells in arithmetic mode and if there's a way to exploit directly the carry chain, i tried with the primitive carry_sum but the compiler ignored it.

thx for you help.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    that kind of resolution is not suitable in an FPGA. You might be able to delay the input at the pin via programmable delays, but not internally.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thx for you answer.

    I looked at the delay programmable parameters on the data sheet just now, and if i understood well it seems it can't reach the resolution i need, i considered the max offset and the number of settings, am i right?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There are some previous threads related to TDC design, e.g. this

    http://www.alteraforum.com/forum/showthread.php?t=4705

    http://www.alteraforum.com/forum/showthread.php?t=27386

    Literature suggests that TDC time resolution in the range you addressed has been implemented in FPGAs.

    As the previous posts show, there are some problems to make Quartus understand your intentions. But it's possible somehow. A more basic problem is making the carry chain work across logic array blocks without larger delay steps.

    As far as I remember, a logic cell primitive, that has it's carry input connected to another logic cell (not a constant) will be set to arithmetic mode.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thanks, i looked at the threads you linked but i didn't find the answer i needed.

    Finally i was able to create a carry chain, but i wasn't able to route the couts to the flip flop inputs. The compiler creates a new cell and connect the cout of the previous cell to the cin of this cell then it passes trhough the lut and it reaches the register, but this is not what i want, since the lut delay propagation is quite longer than the cin-cout's one. Since i saw in literature there are implementations of tapped delay line exploiting the carry chain of cyclone II devices, i wonder how they were able to connect the cout directly to the flip flop. Even taking a look at the datasheet, it seems there's not a route between the cout and the flip flop of the cell. I saw xilinx architectures include a route trhough a mux to connect cout to the cell register. Moreover the guidelines of the primitive carry_sum indicate that it's not possible to connect a cout to an output pin so i desume the carry chain is just dedicated to internal use without the possiblity to read its values through a flip flop.

    I would like to have a confirm or less about this point.

    Thx for your patient, best reguards!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Obviously, the carry chain doesn't directly connect to registers. I understand, that the designs described in literature connect it indirectly, as input to an arithmetic expression. I can't give you detailed how-to instructions, but the literature doesn't look like describing fake designs, you just have to find out how they did.