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Altera_Forum's avatar
Altera_Forum
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14 years ago

delay line

Hello, i'm not expert about fpga so i'd like to read some hints from more expert users. I need to create a delay line on cyclone II, i will use it to implement a flash tapped delay line based time...
Altera_Forum's avatar
Altera_Forum
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14 years ago

There are some previous threads related to TDC design, e.g. this

http://www.alteraforum.com/forum/showthread.php?t=4705

http://www.alteraforum.com/forum/showthread.php?t=27386

Literature suggests that TDC time resolution in the range you addressed has been implemented in FPGAs.

As the previous posts show, there are some problems to make Quartus understand your intentions. But it's possible somehow. A more basic problem is making the carry chain work across logic array blocks without larger delay steps.

As far as I remember, a logic cell primitive, that has it's carry input connected to another logic cell (not a constant) will be set to arithmetic mode.