defining pinout in Cyclone3 to EPCS

I guess, you refering to this statement in QuartusHandbook

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Board-Level Design for an EPCS Device

You must connect the EPCS device to the FPGA as described in the Altera

Configuration Handbook. No other connections are necessary.

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It's about hardware design, not Quartus settings. An AS configuration device uses dedicated resources and needs no entries in Assignment Editor or Pin Planner. Just select AS configuration scheme in Device Options.

I found the solution site of Altera:

solution

In Cyclone® III devices, the EPCS controller does not automatically assign its output pins to the dedicated configuration pins on the FPGA. Instead, the output pins are exported to the top level design, giving users the flexibility to connect to any EPCS devices.

Therefore, in order to use the EPCS Configuration Controller the pins must be assigned manually, and the following settings must be made the Quartus® II software.

Please follow these steps:

1. Choose settings from the assignments menu

2. Click device and pin options from the Device category

3. Click dual-purpose pins and then make the following changes:

Data[0] -> Use as regular I/O

Data[1] -> Use as regularr I/O

DCLK -> Use as regular I/O

FLASH_nCE/nCS0 -> Use as regular I/O

You must check the device pin-out file for the cyclone iii (http://www.altera.com/literature/lit-dp.jsp?category=cyc%203&showspreadsheet=y)device which you are using to make the following pins assignments:

data0_to_the_epcs_controller -> DATA0

sdo_from the_epcs_controller -> DATA1,ASDO

dclk_from_epcs_controller -> DCLK

sce_from_the_epcs_controller -> FLASH_nCE

Actually, AS configuration itself is operational, if an EPCS device is connected and the correct MSEL pin-strapping is provided. Cause the FPGA is unconfigured when reading the configuration, the above settings are meaningless so far. The purpose of the quoted solution isn't explicitely said, I think.

The Pin options may be important for access to the EPCS device at runtime, e. g. when performing a configuration update through NIOS or embedding SFL in the design. Indirect AS programming through JTAG by default SFL image however is also possible without any settings in Quartus design.

P.S.: Considering the problem related to the quoted solution, it's clear that it's dedicated to runtime access to EPCS (e.g. through SFL MegaFunction).

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Why does my Cyclone III FPGA fail to access the EPCS device using the EPCS Controller module?

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Thank you for your quick respond. I indeed didn't mark that my system based on NIOS2 design and included EPCS controller.

Any way it works.