Honored Contributor
Honored ContributorActually, AS configuration itself is operational, if an EPCS device is connected and the correct MSEL pin-strapping is provided. Cause the FPGA is unconfigured when reading the configuration, the above settings are meaningless so far. The purpose of the quoted solution isn't explicitely said, I think.
The Pin options may be important for access to the EPCS device at runtime, e. g. when performing a configuration update through NIOS or embedding SFL in the design. Indirect AS programming through JTAG by default SFL image however is also possible without any settings in Quartus design. P.S.: Considering the problem related to the quoted solution, it's clear that it's dedicated to runtime access to EPCS (e.g. through SFL MegaFunction). --- Quote Start --- Why does my Cyclone III FPGA fail to access the EPCS device using the EPCS Controller module? --- Quote End ---
