Hello Intel Community, I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resource...
Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can.
For MAX 10 devices, we recommend driving the PLL input from the dedicated clock input pins (CLK[0..7]p/n). These pins are directly connected to the device clocking resources and are intended for PLL reference clocks.
Regarding the exact physical pin numbers, you can check using the MAX 10 device pinout file or Quartus® Prime Pin Planner for the specific device OPN that you used.
I have previously reviewed this documentation, which is why I was careful when selecting the pins. For my design, I selected J12 as the input and K4 as the output, as shown in the image below.
However, during compilation, I am still getting the following errors/warnings:
Warning (15055): PLL "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Info (15024): Input port INCLK[0] of node "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" is driven by PIXCLK~inputclkctrl which is OUTCLK output port of Clock control block type node PIXCLK~inputclkctrl
Warning (15064): PLL "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" output port clk[0] feeds output pin "PIXCLK_INV~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Even after checking the datasheet, I still cannot figure out which specific external pins are the dedicated PLL inputs and outputs for this particular part number (10M02SCM153C8G) that would eliminate these warnings.
Could you please explicitly point out those exact physical pins for me? The reference material you provided seems to be a general guideline for the entire MAX 10 family, rather than specific to this package(10M02SCM153C8G).
Additionally, I would like to ask about the symbols on the pins in the TOP VIEW diagram. There are symbols indicating positive-edge and negative-edge pulses—do these carry a specific technical meaning?
In my case, the clock enters through J12 as a negative-edge pulse, and I need to invert it to a positive-edge pulse before passing it to C0 and C1, which is different from the symbol shown on the J12 pin.
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