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Altera_Forum
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10 years ago

Dedicated Clock Input Pins in Arria V

Good day.

There is one question about “dedicated clock pins CLK[23..0]p,n”. In pin connection guidelines it is stated that these pins are dedicated positive and negative clock input pins, that can also be used for data inputs. But in latest PINOUT file these pins described as I/O. For example: Bank 3D VREFB3DN0 io CLK7n DIFFIO_RX_B68n DIFFOUT_B68n AD17 DQ9B.

Can someone explain me if these pins can be used as regular I/O's(bidir) or only as inputs?:confused:

Best Regards,

Serhii Elert

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Elert,

    Basically, the dedicated clk pins (CLK[0:23]p) are mainly used to connect to the plls. Those are the special function pins.

    For your question on whether they can be use as bidir or input pins. Yes, you can do so. All pins works as GPIO but occassionally they are tied to some special functions as you mentioned in the DIFFIO (differential pins) or CLK (for dedicated clock pin)
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Definitely no problem using as input as that is clear in the PCG. To be certain it can be used as output, perhaps you might want to create a reg and set it to output to the pin and see if Quartus allows you to compile it. if it can, i should be no problem as bidir.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Based on my understanding on dedicated clock input pins, generally they can only be used as input because it does not have additional output buffer connected to the same pin. This can helps to reduce the input load seen by the external signal. It is kind of weird to see the pin connection guide label dedicated clock input as IO. It might be a typo. It is recommended for you to try with nicejob's advice to double check with Quartus II.