declaring multiple packed array dimensions is a SystemVerilog feature.

cause: Error (10839): Verilog HDL error ***: declaring multiple packed array dimensions is a SystemVerilog feature.

description: 1. When I build a project with Quartus II version 14.1, there accurs the above problem.

Then I select "SystemVerilog" in Settings->Copiler Settings->Verilog version in Quartus II, the problem remains.

2. How should I solve this problem without modifying the codes?

Must I use synplify to generate .vqm?