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Altera_Forum
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16 years ago

declaring global objects is a SystemVerilog feature?

Hello, I'm quite new to FPGA design, and the Altera tools. I'm trying to work with a dev kit called the MotionFire, which contains a Cyclone III. When working with kits, the first step for ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Could be a bug in Quartus 9.1.

Try a newer versions of Quartus, if possible.

Or maybe it's an issue with the project settings.

In Analysis & Synthesis settings for Verilog, check what flavor of Verilog is set as default.