DECA MAX 10 ADC1/ADC2 via SMA – simultaneous or multiplexed?

Simultaneous sampling on ANAIN1 / ANAIN2 — the key architectural fact

The MAX 10 dual ADC devices feature two independent ADC hard IP blocks, each with its own dedicated analog input pin (ANAIN1 and ANAIN2). For dual ADC devices, each ADC block supports one dedicated analog input pin and up to 8 dual function pins. If you use both ADC blocks, you can use up to two dedicated analog input pins and 16 dual function pins. For simultaneous measurement, you can use only the dedicated analog input pins in both ADC blocks, because the package routing of both dedicated analog pins is matched. Single or Dual ADC Devices This matched routing is the critical point for your phase accuracy requirement.

For dual function pins, the routing latency between the two ADC blocks may cause data mismatch in simultaneous measurement Single or Dual ADC Devices — so stick exclusively to ANAIN1 and ANAIN2 for your two voltage/current sense inputs.

Use the Modular Dual ADC Core IP for synchronization

For simultaneous measurement, use the Modular Dual ADC Core IP core. Single or Dual ADC Devices The Modular Dual ADC Core IP core lets you control both ADC hard IP blocks with a single IP instance. For the analog input pins (ANAIN1 and ANAIN2) in both ADC hard IP blocks, the measurement is synchronous. For the dual function input pins, there are some measurement timing differences caused by routing latency. Modular ADC Core and Modular Dual ADC Core IP Cores This confirms that ANAIN1/ANAIN2 with the Dual ADC Core is the right path for phase-coherent acquisition.

The synchronization mechanism works as follows: the dual ADC synchronizer core performs synchronization handshakes between the two ADC control cores in the Modular Dual ADC Core IP core. The peripheral clock domain is asynchronous to the ADC PLL clock domain in the ADC control core. A control event from the ADC hard IP block can appear at the peripheral clock domain at the same time, or with a difference of one peripheral clock between ADC1 and ADC2 control cores. Dual ADC Synchronizer Core To avoid the condition where ADC1 begins conversion earlier or later than ADC2, the ADC control core performs a synchronization handshake using the dual ADC synchronizer core. An ADC control core asserts a sync_valid signal when it detects an ADC PLL clock domain event. The dual ADC synchronizer core asserts the sync_ready signal after it receives sync_valid signals from both ADC control cores. After sync_ready is asserted, both ADC control cores proceed to their next internal state. Dual ADC Synchronizer Core

ADC specs relevant to your application

12-bit resolution — the basic function is to provide a 12-bit digital representation of the analog signal being observed. MAX 10 FPGA Device Architecture

Normal mode supports a cumulative sampling rate of up to 1 MSPS. MAX 10 FPGA Device Architecture At 1 MSPS per channel, you have well over 10× oversampling at your 100 kHz signal bandwidth, which gives you good margin for phase computation.

Temperature sensing mode monitors at up to 50 ksps; in dual ADC devices, only the first ADC block supports this mode. MAX 10 FPGA Device Architecture For your use case you'll be in normal mode only, so this is not a concern.

Clock source — important constraint

The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path — you cannot change this clock path. ADC Clock Sources You can only use the PLL C0 counter to connect to the ADC reference clock pin. MAX 10 FPGA Design Guidelines In dual ADC mode, both ADC instances must share the same ADC clock setting. ADC Clock Sources This shared clock is what underpins the synchronous sampling on the dedicated pins.

DECA board connectivity

On the DECA board (Arrow), the ADC SMA inputs map directly to the dedicated analog input pins. J18 and J19 are SMA inputs connected to the two FPGA analog-to-digital converter (ADC) dedicated inputs. MAX 10 FPGA Development Kit User Guide So your two measurement channels connect cleanly to ANAIN1 and ANAIN2 via J18/J19 — exactly the pins that support matched-routing simultaneous sampling.

Design guideline reminder

Disable all JTAG operation during ADC sampling — the ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation. MAX 10 FPGA Signal Integrity Design Guidelines Also, Altera recommends tying REFGND to the GND pin with an isolating ferrite bead for best ADC performance. MAX 10 FPGA Device Family Pin Connection Guidelines

Bottom line for your application: Use ANAIN1 (J18) and ANAIN2 (J19) exclusively, instantiate the Modular Dual ADC Core IP, and run in normal mode at your desired sample rate. The dedicated pin routing is matched and the synchronizer core ensures both ADC blocks start conversion simultaneously — giving you the channel-to-channel phase coherence your impedance measurement requires. The 1 MSPS rate gives you ample headroom at 100 kHz.