DE2i-150 - HSMC THDB-ADA Daughter Card (Analog to Digital Converter)

If you download the software/installation, you will find the schematic for the board.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=278

The users manual has some hardware pin mappings in the appendix, though I don't recall if it has the DE2i-150 listed. I doubt it.

You will need to make a spreadsheet of the HSMC connector pin numbers, along with the DE2i-150 pin numbers and the AD/DA pin numbers.

Take a look at the schematics of your respective boards and see if you can figure it out. If you get stuck, ask.

I've been helping another forum user get this board working with a Cyclone III Starter Board. The first step I had him do was to create a spreadsheet; with HSMC pin number, FPGA pin number, VCCIO bank, and pin function,

and then the corresponding pins on the AD/DA board.

WARNING: The AD/DA board uses a non-standard HSMC connector that is flipped relative to the HSMC connector and has more pins; the HSMC has 160 pins, whereas the AD/DA connector has 180 pins (the extra pins are the ones between the differential pairs on the HSMC connector).

The AD/DA card uses 3.3V logic levels. The Cyclone III interface is fixed at 2.5V. If the DE2i-150 can program (jumper options) the VCCIO to the HSMC, then you can use either 3.3V or 2.5V.

Find the schematics for both the AD/DA board and your DE2i-150 and you'll have enough info to get started.

Cheers,

Dave

I don't think my post from yesterday went through, so I'll try a short post this time.

I went through and found all the pins for the ADC Channel A.

I assigned the following signals:

Power

Enable

Clock

And made ports to receive:

Data bits (14)

Overflow

I made a simple program to read the data bits and display them using the on board LEDs from the DE2i-150.

For some reason, I smelled a burning odor and immediately removed power. The Daughter card seemed to be burning up. I'm not sure why, we were using the default 2.5V from the HSMC. Any inputs?

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For some reason, I smelled a burning odor and immediately removed power. The Daughter card seemed to be burning up. I'm not sure why, we were using the default 2.5V from the HSMC. Any inputs?

--- Quote End ---

What did you assign unused I/O to on the FPGA? Perhaps you created a driver conflict between FPGA signals and AD/DA signals. You should always defined *all* I/O connections so that you make wise decisions about unused signals.

Some of the DE2 series boards are designed to load optional 100-ohm termination resistors. You should also check if any need to be *removed*.

Cheers,

Dave

Sorry, that was in my longer explanation that did not get posted...lol

I assigned port B of the ADC to be disabled, via the OEB pin.

I have no idea if this thing is fried, I see no obvious signs after a visual inspection. I will go through and assign every pin on there and see if I still smell this odor. If I do, I think I'm done with it.

Is there a recommended clock frequency when working with this Daughter Card?

This was the pin assignment that I did:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8575

hi,

The DAC on the ADA board has an update rate of 125MSPS , Which is its sampling frequency. But am not sure if the ADA board has to be clocked at that rate in case i am using the DAC.

Any information regarding the clocking of the ADA board will be helpful.

Thank You.

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The DAC on the ADA board has an update rate of 125MSPS , Which is its sampling frequency. But am not sure if the ADA board has to be clocked at that rate in case i am using the DAC.

Any information regarding the clocking of the ADA board will be helpful.

--- Quote End ---

The information you need should be in the DAC data sheet. The part is specified to run at up to 125MHz, but there is nothing to stop you running it slower.

I'd recommend starting at a lower clock frequency, so that the timing constraints are easier to meet. Then you can probe the signals and see what the actual clock-to-output delays on the board is. Then you can incrementally increase the sampling frequency (and the corresponding constraints) until you either reach 125MHz, or timing violations start to occur.

Cheers,

Dave

Is there any way to test the ADA_THDB board without interfacing it without the cyclone 3 starter kit ? Am yet to order the starter kit and I want to verify the ADA board before the starter kit arrives.

I mean is there any independent means by which we can test it's functioning?

Thanks n Advance!

--- Quote Start ---

Is there any way to test the ADA_THDB board without interfacing it without the cyclone 3 starter kit ? Am yet to order the starter kit and I want to verify the ADA board before the starter kit arrives.

I mean is there any independent means by which we can test it's functioning?

--- Quote End ---

Not really. The DAC needs data from somewhere and the ADC data needs to go somewhere. That "somewhere" is via the HSMC connector which is designed to interface to an Altera development kit. So you're pretty much stuck waiting for a development kit.

Cheers,

Dave

Hi ,

In the ADA feature it specifies that the board has clock source of 100 Mhz . The pdf has been attached for reference!

The feature set of the ADA is listed below:

1. Dual AD channels with 14-bit resolution and data rate up to 65 MSPS

2. Dual DA channels with 14-bit resolution and data rate up to 125 MSPS

3. Dual interfaces include HSMC and GPIO, which are fully compatible with Cyclone III Starter

Kit and DE1/DE2/DE2_70/DE2_115/DE3/DE4, respectively

4. Clock sources include oscillator 100MHz, SMA for AD and DA each, and PLL from either

HSMC or GPIO interface

5. AD converter analog input range 2V p-p range.

6. DA converter output voltage range 2V p-p range.

7. DA and AD converters do not support DC signaling

So does it imply the board has its own clock? if so how do we enable it?

Thanks!