Forum Discussion
Honored ContributorDE2 Audio Codec Programming
Hi,
I am engg student.I are working on SOPC baesd speech to text conversion.I am confused with how to to program audio codec for Audio to Digital conversion for input from microphone and give it to FPGA.25 Replies
Altera_Forumi am looking module for my project too
- Altera_Forum
Hi,
I'm not quite sure, but I think you can use the SPI SOPC module to build up the communication path to the CODEC Chip. . . . Maik - Altera_Forum
i use Audio Codec but i dont understand how it config
- Altera_Forum
Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet.
I have tested this on both the DE1 and DE2 boards. I hope you find it useful, but there is no warranty implied! Jim - Altera_Forum--- Quote Start --- Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet. I have tested this on both the DE1 and DE2 boards. I hope you find it useful, but there is no warranty implied! Jim --- Quote End --- thanks for sending the VHDL code ,this code utilise the clock of 24Mhz i have 50 MHz crystal in my DE2 board so please suggest the change in the code thank u again
- Altera_Forum
Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference.
- Altera_Forum--- Quote Start --- Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference. --- Quote End --- Dear sir i have done the intitialization of the codec registor by using the 50Mhz crystal i am getting ack , sir i am not getting whether xclk i.e the master clock of codec must require to fetch the data from LR chanal please sugest the logic for sound fetching & more about the DSP mode of codec.
- Altera_Forum
Hello, you should read the WM8731 datasheet. All the details you need are in there.
- Altera_Forum--- Quote Start --- Hi, I am engg student.I are working on SOPC baesd speech to text conversion.I am confused with how to to program audio codec for Audio to Digital conversion for input from microphone and give it to FPGA. --- Quote End --- Go throw the data sheet of codec configure the codec registor ,the sound digital data will be available on ADCDAT of codec
- Altera_Forum
Thanks for your vhdl code jjclark. It is really helpful.
I have set it up and it works perfect. I am now trying to feed line in from the audio codec. But am having trouble, as the output has a lot of noise. Im guessing its got something to do with my timing? Would you be able to attach an example of line in? That would be very appreciated.
