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Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference.
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Dear sir i have done the intitialization of the codec registor by using the 50Mhz crystal i am getting ack , sir i am not getting whether xclk i.e the master clock of codec must require to fetch the data from LR chanal please sugest the logic for sound fetching & more about the DSP mode of codec.
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