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Honored Contributor
Honored ContributorDE2-115 and IP Cores
I am doing development, which is intended for a DE2-115 target.
While waiting for the board arrival, I downloaded Quartus Prime Lite Edition 17.1 and began experimenting with developing FPGA vhdl code, a NIOS II Gen 2 and Ethernet TSE architecture, and some NIOS II 'C' code. After compiling the design (with no errors) I was going through the warnings and noticed the following: Warning (12188): Intel FPGA IP Evaluation Mode feature is turned on for the following cores Warning (12190): "Nios II Processor (6AF7_00A2)" will use the Intel FPGA IP Evaluation Mode feature Warning (12190): "Triple-Speed Ethernet" will use the Intel FPGA IP Evaluation Mode feature Warning (265072): Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature Warning (265073): Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature TSE_MAC Warning (265074): The Triple Speed Ethernet MegaCore MAC function will be disabled after time-out is reached Warning (265073): Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature Nios II Processor Warning (265074): The reset input will be asserted when the evaluation time expires Warning (265069): Megafunction that supports Intel FPGA IP Evaluation Mode feature will stop functioning in 1 hour after device is programmed Info (265071): Evaluation period of megafunction that supports Intel FPGA IP Evaluation Mode feature can be extended indefinitely by using tethered operation. Does this mean the Nios II processor and the Ethernet TSE core are unavailable for use with the board? Is this a function of using Quartus Prime Lite 17.1 (vs Quartus II Web Edition 9.1 sp2 in the DE2-115 documentation on the SystemCD)? What are the restrictions of "Evaluation Mode". Was is required to overcome them?
