DE1-SoC problem with tree please HELP!!

Question

I’m trying to configure a qsys system with hps and vga control to see the Linux environment and create a c program that can obtain the memory mapped signal and print on the vga. The steps that I did are: -Create a golden top and qsys system -Create a rbf with convert file formats(no compression) -Download de Ubuntu from altera and prepare de sd with that image -Download de   soc_system_board_info.xml and hps_common_board_info.xml files from https://releases.rocketboards.org/release/2014.06/gsrd/ghrd/ -Create a dtb in two steps: $ sopc2dts -i sistema.sopcinfo -b soc_system_board_info.xml -b hps_common_board_info.xml -o socfp
ga.dts --bridge-removal all --clocks $ dtc -I dts -O dtb -o socfpga.dtb -f socfpga.dts   There are some errors: $ sopc2dts -i sistema.sopcinfo -b soc_system_board_info.xml -b hps_common_board_info.xml -o socfpga.dts --bridge-remova
l all --clocks Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component alt_vip_itc_0 of class alt_vip_itc is unknown Component pll_0 of class altera_pll is unknown Component pll_6553600 of class altera_pll is unknown Component reset_controller_0 of class altera_reset_controller is unknown Component reset_controller_1 of class altera_reset_controller is unknown Component video_pll_0 of class altera_up_avalon_video_pll is unknown MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null Component alt_vip_itc_0 of class alt_vip_itc is unknown Component pll_0 of class altera_pll is unknown Component pll_6553600 of class altera_pll is unknown Component reset_controller_0 of class altera_reset_controller is unknown Component reset_controller_1 of class altera_reset_controller is unknown Component video_pll_0 of class altera_up_avalon_video_pll is unknown MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null   $ dtc -I dts -O dtb -o socfpga.dtb -f socfpga.dts  ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "pll_0"
 
ERROR (phandle_references): Reference to non-existent node or label "led_pio"
 
ERROR (phandle_references): Reference to non-existent node or label "led_pio"
 
ERROR (phandle_references): Reference to non-existent node or label "led_pio"
 
ERROR (phandle_references): Reference to non-existent node or label "led_pio"
 
Warning: Input tree has errors, output forced       -Remplace the socfpga.dtb and soc_system.rbf from sd for my files.   The MSEL is all to 000000 and I plug in the sd and the system start to kernel but has an error https://alteraforum.com/forum/attachment.php?attachmentid=13839&amp;stc=1    https://alteraforum.com/forum/attachment.php?attachmentid=13840&amp;stc=1  https://alteraforum.com/forum/attachment.php?attachmentid=13841&amp;stc=1    https://alteraforum.com/forum/attachment.php?attachmentid=13842&amp;stc=1        Any idea? Tanks!, Juan.

altera_forum · Answer

Hello, for the VIP IP in the FPGA, you will need to add to the device tree manually (as far as I know, the device tree generator does not recognize the VIP IP). To obtain the VIP device tree declaration, you can use the device tree file that is included in the DE1-SoC MTL2 package.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=204&no=930&partno=4

I've attached the relevant dtsi file here - you can modify or merge with your own dts file

socfpga.dtsi.txt22 KB

altera_forum · Answer

Thank!.. but I have a VIP declaration in device tree  --- Quote Start ---  Hello, for the VIP IP in the FPGA, you will need to add to the device tree manually (as far as I know, the device tree generator does not recognize the VIP IP). To obtain the VIP device tree declaration, you can use the device tree file that is included in the DE1-SoC MTL2 package.  http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&amp;categoryno=204&amp;no=930&amp;partno=4  I've attached the relevant dtsi file here - you can modify or merge with your own dts file  --- Quote End ---   alt_vip_vfr_0: vip@0x100000000 {
				compatible = "ALTR,vip-frame-reader-14.0", "ALTR,vip-frame-reader-9.1";
				reg = &lt;0x00000001 0x00000000 0x00000080&gt;;
				clocks = &lt;&amp;video_pll_0 &amp;pll_0&gt;;
				clock-names = "clock_reset", "clock_master";
				max-width = &lt;1024&gt;;	/* MAX_IMAGE_WIDTH type NUMBER */
				max-height = &lt;768&gt;;	/* MAX_IMAGE_HEIGHT type NUMBER */
				bits-per-color = &lt;8&gt;;	/* BITS_PER_PIXEL_PER_COLOR_PLANE type NUMBER */
				colors-per-beat = &lt;4&gt;;	/* NUMBER_OF_CHANNELS_IN_PARALLEL type NUMBER */
				beats-per-pixel = &lt;1&gt;;	/* NUMBER_OF_CHANNELS_IN_SEQUENCE type NUMBER */
				mem-word-width = &lt;128&gt;;	/* MEM_PORT_WIDTH type NUMBER */
			}; //end vip@0x100000000 (alt_vip_vfr_0)
		}; //end bridge@0xff200000 (hps_0_bridges)  I'm not worried for the error messages because som of them not have a connection with the hps. There are something wrong in other part of the code.

altera_forum · Answer

I add a *dtb file in txt format generated by the commandsopc2dts -i sistema.sopcinfo -b soc_system_board_info.xml -b hps_common_board_info.xml -o socfpga.dts --bridge-remova
l all --clocks. You can check that is there a VIP declaration.

altera_forum · Answer

Hi, I'm worried about this. Do I have to recompile linux? Is this mandatory?

--- Quote Start ---

Hello, for the VIP IP in the FPGA, you will need to add to the device tree manually (as far as I know, the device tree generator does not recognize the VIP IP). To obtain the VIP device tree declaration, you can use the device tree file that is included in the DE1-SoC MTL2 package.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=204&no=930&partno=4

I've attached the relevant dtsi file here - you can modify or merge with your own dts file

--- Quote End ---

altera_forum · Answer

Hi,

I think the situation is this:

When you created an IP component in qsys his definition is in your_qsys.sopcinfo but not is in soc_system_board_info.xml and hps_common_board_info.xml so the sopc2dts command can't create a component and the device tree is uncomplete.

Is this true? editting the xml files mut solve the problem.

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DE1-SoC problem with tree please HELP!!

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