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Altera_Forum
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8 years ago

DE1-SoC problem with tree please HELP!!

I’m trying to configure a qsys system with hps and vga control to see the Linux environment and create a c program that can obtain the memory mapped signal and print on the vga. The steps that I d...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thank!.. but I have a VIP declaration in device tree

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Hello, for the VIP IP in the FPGA, you will need to add to the device tree manually (as far as I know, the device tree generator does not recognize the VIP IP). To obtain the VIP device tree declaration, you can use the device tree file that is included in the DE1-SoC MTL2 package.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=204&no=930&partno=4

I've attached the relevant dtsi file here - you can modify or merge with your own dts file

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alt_vip_vfr_0: vip@0x100000000 {
				compatible = "ALTR,vip-frame-reader-14.0", "ALTR,vip-frame-reader-9.1";
				reg = <0x00000001 0x00000000 0x00000080>;
				clocks = <&video_pll_0 &pll_0>;
				clock-names = "clock_reset", "clock_master";
				max-width = <1024>;	/* MAX_IMAGE_WIDTH type NUMBER */
				max-height = <768>;	/* MAX_IMAGE_HEIGHT type NUMBER */
				bits-per-color = <8>;	/* BITS_PER_PIXEL_PER_COLOR_PLANE type NUMBER */
				colors-per-beat = <4>;	/* NUMBER_OF_CHANNELS_IN_PARALLEL type NUMBER */
				beats-per-pixel = <1>;	/* NUMBER_OF_CHANNELS_IN_SEQUENCE type NUMBER */
				mem-word-width = <128>;	/* MEM_PORT_WIDTH type NUMBER */
			}; //end vip@0x100000000 (alt_vip_vfr_0)
		}; //end bridge@0xff200000 (hps_0_bridges)

I'm not worried for the error messages because som of them not have a connection with the hps. There are something wrong in other part of the code.