--- Quote Start ---
i have a de0 nano board
i have a design that consist of a number of components that are composed of multiple components (components inside components inside components).
the problem is that when a signal that must be generated from a low level component and advance to the output of the full design it comes out with half of the voltage that it must have in normal designs i.e(1.6v instead of 3.3v)
can any one help
--- Quote End ---
Your problem can not be due to the design hierarchy, you most likely have a driver conflict at the board-level. The difference between your designs is that one does not produce the driver conflict, while the hierarchical design does.
You can confirm that there is no problem with your design by first simulating it in Modelsim.
Another potential reason for reading an incorrect voltage with a voltmeter, is that rather than being a single logic level, you are some how probing a square wave. If you can probe with an oscilloscope, you can eliminate that as being the issue.
Cheers,
Dave
Honored Contributor
