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Altera_Forum
Honored Contributor
Honored ContributorDDR3 Uniphy hang
Hi,
I got issue with regards to running single write in sample project using DDR3 uniphy. I am using Cyclone V GT. The projects compiled ok, timing requirements are met, fully constrained(refer to attached photo). I was able to programmed successfully in Cyclone V gt Dev Kit. I was able to download the elf file using Nios Eclipse. The problem is when I run the program, it hangs at code portion "IOWR(UNIPHY_DDR3_BASE,DDR_write_OFFSET_ADDRESS,write_data)". The parameters in IOWR are all correct. Do you have any idea what is causing this issue. I attached the qsys photo and also the NIOS II eclipse console for your reference. Regards, Aris5 Replies
Altera_Forumhave you done any successful read/writes?
do you know if the DDR3 is completing and passing calibration? you should run the UniPHY Status signals out of Qsys as a conduit, and run them to LEDs/STP- Altera_Forum
Hi,
No successful r/w so far. Been trying to do a single write to a single address. Tried to write 12345678 hex to an address 00000080 but it does not continue. Tried to look at signal tap, and can see from signal tap the data 12345678, but the address is 00000040 instead of 00000080. Tried to use different address: inputted 00000010 but signatap shows 00000008. Regards - Altera_Forum
did you take a look at the status signals as i mentioned? this will tell you if the calibration has passed
- Altera_Forum--- Quote Start --- did you take a look at the status signals as i mentioned? this will tell you if the calibration has passed --- Quote End --- Hi, I just try to monitor the afi_cal_success and it is always low. afi_cal_fail is always high.. seems like the calibration is not ok. What should be the cause of this? Any thing I should do?
- Altera_Forum
if you run the EMI Toolkit, you'll get visibility into what specifically is causing the problem
you might also try and back off the frequency
