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Altera_Forum
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10 years ago

DDR3 Timings Violation - MAX10 NEEK

Hi there, I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Even the most aggressive optimization gives timing violations. Strange...