Occasional Contributor
Regular ContributorHi Seadog,
According to the Report DDR, the timing violation is not in the EMIF IP.
It's within the EMIF block and other.
Do you used the PLL IP core?
If yes, can you remove it? Because the EMIF can work without it.
Regards,
Adzim
Occasional ContributorAccording to the Report DDR, the timing violation is not in the EMIF IP.
It's within the EMIF block and other.
Does this really matter? The timing violation is not in my RTL code, it is in the vendor-provided memory controller code.
Do you used the PLL IP core?
If yes, can you remove it? Because the EMIF can work without it.
The only PLL I know of is in the PHY; it provides the clock used to interface to the memory, as well as the clock used for the system (Avalon) interface. I don't know how to exclude that PLL, but something has to generate those clocks.
I am uploading a Word doc with the EMIF configuration details.
