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Altera_Forum
Honored Contributor
Honored ContributorDDR3 SDRAM controller - pll_ref_clk
Hi,
I am using Quartus 13.1 and DDR3 SDRAM controller with hard memory controller enabled in the QSYS. The DDR3 controller's PLL reference clock frequency is set to 125Mhz and I was using a clock source of 125MHz with no issue of building the project. However, when I try to change it to an Altera PLL to generate this reference clock input, it gives me the following critical error. Does anyone know why? or all PLL reference clock need to come from a clock source? Qsys_ddr3a_p0_pin_map.tcl: failed to find PLL reference clock Can't fit design in device1 Reply
Altera_ForumHello NJ_paddler, here are a couple of things to try. Here is the link to your error from Altera's website:
http://www.altera.com/support/kdb/solutions/rd05282014_665.html First try the approach that they give on that link. If that doesn't work, I know that I have had issues in placing PLL's in the past. The way that I have got around it in the past is by implementing an altclkctrl megafunction placed in between the clocked input pin and the PLL as seen in this link: http://www.altera.com/support/kdb/solutions/rd03302012_430.html Best of luck to you! Let me know if neither of those approaches work.
