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Altera_Forum's avatar
Altera_Forum
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10 years ago

DDR3 Memory errors but passes Calibration

Hi We are getting intermittent memory read errors from our DDR3 SDRAM Controller with UniPHY hmc in a Cyclone V Using the EMIF toolkit we can run calibration on the memory and it passes every time...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I have a similar problem, using the same tools, IP and 300MHz clock, on a Cyclone V Altera development board. Intermittent read (or possibly write in my case) errors from the DDR3. So, a platform that clearly works without errors - as confirmed with the sample memory test projects supplied.

I've not got to the bottom of it yet (early days) but clearly my implementation is responsible.

Have you tried your hardware with the example design that's offered to you when you run the IP configuration tool? I could get that working.

I will post any of my findings here. It's not a high priority here so that may be some time... sorry.

Cheers,

Alex