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Altera_Forum
Honored Contributor
Honored ContributorDDR3 HMC operation rate
Hi,
I am confused about the DDR3 HMC operation rate of Cyclone V. The handbook says that "full rate designs might have difficulty in closing timing. Consequently,for high frequency memory interface designs, Altera recommends that you use half-rate or quarter-rate UniPHY IP and controllers." and "For this reason, Altera High-Performance Controller II and UniPHY IPs do not support full rate designs using the DDR3 SDRAM interface. However, the DDR3 hard controller in Arria® V devices supports only full rate." Since altera don't recommend to use full rate,why Cyclone V or Arria V device can only operation at full data rate (HMC)? and may the HMC have problem in closing timing ? do users take risks when use this device? how to solve this problem? looking forward your reply.3 Replies
Altera_Forumlooking forward your help.
- Altera_Forum
I also noticed these words. Does it mean high risk to use HMC in Cyclone V? Is there any solution to this? Thanks.
- Altera_Forum--- Quote Start --- I also noticed these words. Does it mean high risk to use HMC in Cyclone V? Is there any solution to this? Thanks. --- Quote End --- It is low risk to use HMC in Cyclone V. The solution is to not operate the MPFE ports using the afi_clk. Instead, use a slower clock (perhaps afi_half_clk, or any other clock in your system).
