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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 critical error

I am use Arria II do do some experimental work using on board DDR3 memory.

I have used DDR3 ALTPHY, I have not export "external_connection" as it seems all the conduit singal is status output, I guess there should be no problem is leave it.(correct me if I am wrong)

I have connect the signal to FPGA pin, and build, the system seems working(I am able to run NIOS software without any problem), however there are few critical warnings I am a bit concerning.

the first one is:

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(495): the port and data declarations for array port "afi_rrank" do not specify the same range for each dimension

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(496): the port and data declarations for array port "afi_wrank" do not specify the same range for each dimension

The second one is:

Critical Warning: ALTMEMPHY IP was generated using a speedgrade of 4, but is being compiled for a speedgrade of 5. Timing analysis may not be valid due to violated timing model assumptions.

Critical Warning: DDR Timing requirements not met

any ideas how could I get rid of these warnings? Thanks for your help in advacne

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I got the same Critical Warnings with a DDR2 design. This is what I did to eliminate them.

    Open the alt_mem_ddrx_controller_st_top.v file. I expect that you will find this line:

    parameter CFG_USE_SHADOW_REGS = 0;

    If you see this line, my guess is that the outputs in question (afi_rrank and afi_wrank) are not being used. In my case, these outputs were not even included by the instantiating module, ddr2_core_alt_mem_ddrx_controller_top.v.

    To make the widths match, find these lines:

    parameter CFG_RRANK_BUS_WIDTH = 0;

    parameter CFG_WRANK_BUS_WIDTH = 0;

    and change them to:

    parameter CFG_RRANK_BUS_WIDTH = MEM_IF_CHIP * (DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH;

    parameter CFG_WRANK_BUS_WIDTH = MEM_IF_CHIP * (DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH;

    Save and compile.