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Altera_Forum
Honored Contributor
14 years agoDDR3 critical error
I am use Arria II do do some experimental work using on board DDR3 memory. I have used DDR3 ALTPHY, I have not export "external_connection" as it seems all the conduit singal is status output, I g...
Altera_Forum
Honored Contributor
13 years agoI got the same Critical Warnings with a DDR2 design. This is what I did to eliminate them.
Open the alt_mem_ddrx_controller_st_top.v file. I expect that you will find this line: parameter CFG_USE_SHADOW_REGS = 0; If you see this line, my guess is that the outputs in question (afi_rrank and afi_wrank) are not being used. In my case, these outputs were not even included by the instantiating module, ddr2_core_alt_mem_ddrx_controller_top.v. To make the widths match, find these lines: parameter CFG_RRANK_BUS_WIDTH = 0; parameter CFG_WRANK_BUS_WIDTH = 0; and change them to: parameter CFG_RRANK_BUS_WIDTH = MEM_IF_CHIP * (DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH; parameter CFG_WRANK_BUS_WIDTH = MEM_IF_CHIP * (DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH; Save and compile.