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Altera_Forum
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15 years ago

DDR3 and fpga orientation

Hi,

We are using ALtera FPGA stratix 4 GX530 ,1932 package industrial component(speed grade3). In the FPGA handbook it is mentioned that in fig 7-18 that banks 1A,1B,1C in left hand side, but in quartus 2 tool in TOP Flip view , the banks are located in right side.Pls inform the right position as soon as possible.

2. we are planning to Interface DDR3 533Mhz with the FPGA, but quartus tool says that 300Mhz only possible. in this case which is better DDR2 400Mhz or DDR3 400Mhz. ?Morever recently is not releasing 400mhz ddr3

3. With newer quatus tool version 10 is it possilble to increase the DDR3 controller speed from 300 to 600Mhz in Stratix4?...

Waiting for your reply..

Regards

vengadesh

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The reason you are seeing the left / right flip is because one diagram is showing you the "die" relationships while the other is showing you the Package relationship.

    The "die" is left / right flipped as it is mounted upside down in the package - thus the name flip chip packaging.

    This is a 'common' problem many before you have faced, and it is a good thing hat you are checking all this out NOW before you lay out your board.

    So both are "correct".

    I do not think that in the I3 speed grade you will be able to get 533 performance.

    DDR2 or DDR3 @ 400 is a good question to ask about.

    If you are designing for the future - then DDR3 will become cheaper as time moves on.

    If you are making a board now for small run sizes, I think that DDR2 is still cheaper.

    Additionally - I believe once you dig in you will find that for DDR3, you will need to "burst" in more rows of data then in DDR2 and if you are jumping about in your data set, this could take longer for the controller in the long run, whereas if you are moving large amounts of sequential data, this might be better for you.

    It all depends.

    You have lots of reading to do on both memory type and some system data flow analysis before you can make that decision.

    With 10.0 - I still think that you will be limited by the I3 speed grade limit - not by the newer tool.

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