DDR2 pin assignment

The Cyclone IV handbook has a section on External Memory Interfaces that I believe is pretty clear on having specific DQ/DQS groups. I don't say that to be mean, but am wondering if it's not clear enough?

I am also a huge advocate of building a framework for the design before building the board. I know that's difficult to do, but I've seen more than enough cases where it costs more time in the end. Again, I don't mean to be mean.

Finally, please file an SR to see if there is any way to disable this check. Since this is probably just a test board now, that might free up any restrictions. Note that Stratix devices have dedicated paths and logic in silicon that absolutely require the pairing of a DQ with its DQS, but looking at the CIV datasheet, I don't see anything similar. It may be this is more of a software check, in which case maybe you can get a workaround. A longshot, but would help if it works. Good luck.