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Altera_Forum
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14 years ago

DDR2 pin assignment

This is a very long shot, probably nobody will answer this, but here I go just in case. In Quartus II 11.1, for an EP4CGX50CF23C7 (F484 package, speed grade 7), I instantiated an altmemphy int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

From what I can tell right now, for every DQS, there are limited options for DQ and DM lines. The problem is that in the board they are scrambled (DQ's for DQS0 are within the options of DQS1 and viceversa), so only a few are 'correct'. I tried relaxing the timing requirements of the memory, and even reducing the frequency, but it makes no difference, the fitter will complain anyway. Even the DMs are swapped. This is completely undocumented from what I've read, only found when synthesizing and fitting (development was backwards due to time constraints).

Does anybody know a way around this ??

My only idea right now is to use the ones I have correct and leave the other pins with pullups. Will complicate the design internally and halve the effective bandwidth and capacity but it is better than nothing.

Regarding the DM (data masks), I figure they can stay low all the time and simply not mask anything, which is fine.

Not sure if there will be an issue regarding the registers in the memory that altmemphy may try to configure... don't know enough about this.

Any info on any of this would be useful.