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Altera_Forum's avatar
Altera_Forum
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16 years ago

DDR2 capture registers in CycloneIII, how to?

Hello,

I'm using the 3c120 Dev. Kit and Quartus II 9.1; I have a DDR2 interface which uses the DQS signals as inputs to capture the data... I get a Critical Warning from the fitter:

"Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os

Info: DQ capture register altddio_bidir:\DQS_P_GEN:0:i_altddio_bidir_dqs|ddio_bidir_0uj:auto_generated|input_cell_h[0] at (72, 17) is not assigned to the adjacent LAB of the corresponding DQ I/O ddr2_dqs[0]~input at (79, 0)"

Searching in this forum I found a similar thread:

i can't post the link here :(, is the first hit you get searching in this forum using keywords: "assigning capture registers, how to?"

So I tried to place the LABs manually using:

set_location_assignment LAB_X79_Y1_N0 -to "altddio_bidir:\\DQS_P_GEN:0:i_altddio_bidir_dqs|ddio_bidir_0uj:auto_generated|input_cell_h[0]"

Now the fitter comes back complaing about another 4, so I add the other 4 to the same location :confused::

set_location_assignment LAB_X79_Y1_N0 -to "altddio_bidir:i_altddio_bidir|ddio_bidir_mvj:auto_generated|input_cell_h[0]"

set_location_assignment LAB_X79_Y1_N0 -to "altddio_bidir:i_altddio_bidir|ddio_bidir_mvj:auto_generated|input_cell_h[1]"

set_location_assignment LAB_X79_Y1_N0 -to "altddio_bidir:i_altddio_bidir|ddio_bidir_mvj:auto_generated|input_cell_l[0]"

set_location_assignment LAB_X79_Y1_N0 -to "altddio_bidir:i_altddio_bidir|ddio_bidir_mvj:auto_generated|input_cell_l[1]"

and now the fitter stops:

"Error: Group of cells has been assigned to a single LAB. Some or all of these cells do not have a specific LE sublocation. The Quartus II software failed to find a legal sublocation for these cells in the LAB"

:eek: This is just a simple design running in this evaluation board, what should I do to get these critical warnings to go away? I kind of expected Altera had tried the DQS approach but all the example designs that come with the Kit are based in the capture clock. BTW if I build the design with the warnings timing looks horrible and the safe sampling window is narrow...

Many thanks in advance,

Regards,

-Ulises

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Ulises,

    You referred to my question from about a year ago. I finally managed to assign the pins and to get rid of the critical warnings. I also played around with a self-made DDR2 controller using a legacy data-path borrowed from Altera's 'standard' DDR2 controller. I did get the same warnings there. So I now let the Quartus compiler and/or the MegaWizard do the initial placing, relying on those two to do it without warnings. Then I backannotate the pins so I can see in the Pin Planner where they have been put and then restrict myself to only swap those locations. Now the Quartus placement isn't always ideal, but it is a good start. You'll learn ...

    Josy
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks Josy,

    That's the question I meant, I can't believe the tools can't sort it out by themselves...I'm trying to understand what you did, struggling a bit...

    How do you do your initial placing? you just build the design without IO location constraints for the DDR IOs so that Quartus choose the more adequate pins for you? If so what next... I'm constrained here to the IO locations in the Evaluation Kit, I can't change that.

    And what do you mean by "Then I backannotate the pins"? I am not used to that therminology :confused:

    Regards,

    -Ulises
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ulises,

    I agree with you to expect the evaluation board to have correct pin assignments, I'm quite sure they are correct.

    Now I never use evaluation boards, they never seem to do what I want, but that's just me...

    Backannotate: select Assignments->Back-Annotate Assignments and then just click OK to accept the suggested 'Pin & Device Assignments'.

    Now if you have an evaluation board I expect that the .qsf of the examples have the IO locations already filled in.

    I just compiled the 'nios' example (which uses the DDR2) from the Quartus 7.2 version of the 3C120 evaluation kit but Quartus II 9.0 SP2 threw an error in the .sdc file. I downloaded the 'upgrade' and tried again: I get the same error and the fitters ends with a 'no fit' message.

    Are you trying such an example? A clear target is easier to comment upon.

    Josy
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Josy,

    I've double checked the pin-out of the Eval Board and uses the recommended Q/S IOs for the DDR2 signals, all seems ok tbh. I've also used the DDR2.QSF file they provide as a template.

    I followed your suggestion and compiled the Nios II example that comes with the eval. Kit, Quartus maps and fits it properly with no critical warnings (I've used Quartus II 9.1), I believe there are no critical warnings because Altera's DDR2 controller doesn't use DQS as input, it uses the capture clock... In my design if I use a capture clock then the critical warnings go away, annoying because I want to use DQS as input...

    Regards,

    -Ulises
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ulises,

    I had the idea that Quartus II for Cyclone III only supports the High Performance DDR2 Controller which uses alt_memphy and that uses the DQS as input strobes. (At least that is what I see in the project on my system).

    Are you using your own controller? We also have our own controller and I tried pairing that to the alt_memphy but I couldn't get things right, so I decided to initially use the HP DDR2 Controller to lay out the pins (using the method I described before) and either put a wrapper around it later or work out what goes wrong (with TimeQuest reporting errors) when using our controller.

    Regards,

    Josy
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Josy,

    We are using our own controller without the alt_memphy, we might need to pair our own ddr2 controller with the alt_memphy module for this to work... the critical warnings seem to be an indication of Quartus not liking what I do with the DQS signals.

    Regards,

    -Ulises