DDR Output Constraining - "too positive" slack

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I gave up with RGMII, most likely will go with GMII PHYs.

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Did you consider adding 1 pipeline cycle and swapping the data for high and low clock edges?

I don't recall all the (r)GMII details, but IIRC you can insert an extra cycle on the transmitter pipeline. The idea is to transmit on the opposite edge of the clock. This way you wouldn't need to delay the clock, because data would naturally be delayed with respect to the clock.