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Altera_Forum
Honored Contributor
Honored ContributorDDR Output Constraining - "too positive" slack
Hi, I hope someone knows the solution to the problem that kept me really busy lately :( I have to connect to an RGMII PHY that has the following parameters: tCLK = 8 (ns) TskewR (Da...
Altera_ForumHonored Contributor
Honored Contributor125MHz should work without a PLL...
