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Honored ContributorDDR input without DPA in Arria II GX
Hello
I am using arria ii gx to communicate with a high speed device. The device is sending DDR data, data with a data clock, dclk. dclk and data are source synchronous. I need to capture the data inside my Arria II GX FPGA, using dclk and separate it into a positive & negative edge streams. The problem is that the skew between dclk and data, by the time they get into the FPGA, is unknown. Thus I want to be able to slide dclk or try different phases of dclk to capture the data. I was able to do this in Xilinx Virtex FPGAs using the iobdelay function, which allowed me to adjust the skew between dclk and data at run time. I want to do exactly the same in Arria II GX but I find no comparable option. I do not have a training pattern so the dpa is out. Can someone suggest a solution? Can I gain the ability to try various phases of dclk for sampling data in Arria II GX? Thanks in advance for your help!!!26 Replies
Altera_ForumHello
Not only the relationship between data and clock, the input frequency of the clock also changes from board to board (max is 500 MHz). :mad: I think Dynamic PLL reconfiguration is an appealing idea, if it is available in Arria II. Thanks a lot for your guidance! Any reference design that I can use?:D Regards,- Altera_Forum
Is the relationship between DCLK and DATA fixed on every board or does it change between boards. Meaning do you just need to determine the relationship once for the design or is every instance of the board going to have something different?
If it is static, you can control the skew with timing constraints. If it is dynamic, One thing you can do is bring DCLK into a PLL. Then you can phase shift the PLL until you get the right sampling position. Jake - Altera_Forum
Thanks for replying!
The device is sending data at 1 GHz with a 500MHz clock (DDR fashion). I want to split it into 4 streams of 250 MHz inside Arria II GX fpga. I am exploring the suggestion of using alt_dq_dqs but I am not sure if I can provide a high speed clock to a DQS pin in Arria II (I am not sure if DQS pins are also routed to regional or global clock trees) Please advice. Thank! - Altera_Forum
What's the data rate? Can offer solutions until we know that.
Jake - Altera_Forum
Thanks for replying!!
But "ALTDQ_DQS" is not supported in Arria II GX? At least that is what the megawizard data sheet says. "ALTMEMPHY" functions generates a whole DDR Memory controller which I don't want. Any more suggestions? - Altera_Forum
There is a "DQS delay chain" in Arria II that you could use to adjust the phase between clock and data dynamically.
