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Honored Contributor
Honored ContributorDDR input without DPA in Arria II GX
Hello I am using arria ii gx to communicate with a high speed device. The device is sending DDR data, data with a data clock, dclk. dclk and data are source synchronous. I need to capture the d...
Altera_ForumHonored Contributor
Honored ContributorIs the relationship between DCLK and DATA fixed on every board or does it change between boards. Meaning do you just need to determine the relationship once for the design or is every instance of the board going to have something different?
If it is static, you can control the skew with timing constraints. If it is dynamic, One thing you can do is bring DCLK into a PLL. Then you can phase shift the PLL until you get the right sampling position. Jake
