DDR input without DPA in Arria II GX

Is the relationship between DCLK and DATA fixed on every board or does it change between boards. Meaning do you just need to determine the relationship once for the design or is every instance of the board going to have something different?

If it is static, you can control the skew with timing constraints.

If it is dynamic, One thing you can do is bring DCLK into a PLL. Then you can phase shift the PLL until you get the right sampling position.

Jake