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Altera_Forum's avatar
Altera_Forum
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8 years ago

DDR II SDRAM Data Mask Pins assignments

I have designed custom PCB in which i have interfaced Cycone III FPGA with DDR II SDRAM. In the designing phase, i assigned the pins with FPGA and synthesize the project. The fitting report was succe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Have you run the 'parameters.tcl' script? It may be failing due to missing I/O constraints to do with the DDR I/O and not because the pin is fundamentally wrong.

You must have run Analysis & Synthesis on your project first. Then, under 'Tools' -> 'Tcl Scripts...' you should have a list of tcl scripts relevant to the IP you have in your design. Run the parameters.tcl script, relevant to the DDR IP in question. This will add 'a load of I/O constraints' (but not specific pin assignments) relevant to the IP you're using. Check the Quartus Constraints File (.qsf) to ensure that running the script has modified it.

Cheers,

Alex