Honored ContributorHi everybody,
When I try to change to 55º the pll clk phase wich affects the ddr address&command signals, the following message appears: Critical Warning: PLL clock must be phase shifted between 72 to 108 degrees more than PLL Then it's impossible for me to expand de data window for the ddr. Any help would be grateful. ifdm
Honored ContributorWhat DDR controller do You use?
Honored ContributorHigh performance controller 2, for the memory A3s56d40ctp
Honored ContributorYou don't need to change any PLL options that are set by HPMC2. The controller creates required clock according to Your memory chip settings and gives differential clock output. You don't need any other PLL to be instantiated.
Honored ContributorI have read for having a more balanced address and command
datapath (setup and hold margin) it's recommended to change the phase of the clk given by the pll used by the ddr controller. I have read that in the app_note www.altera.com/literature/hb/external-memory/emi_tut_ddr.pdfHonored ContributorI suggest trusting the controller created PLL and don't change the settings. If the hardware is OK, it works fine.
