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Honored Contributor
Honored ContributorDDR Data window
Hi everybody, When I try to change to 55º the pll clk phase wich affects the ddr address&command signals, the following message appears: Critical Warning: PLL clock must be phase shifted ...
Altera_ForumHonored Contributor
Honored ContributorI have read for having a more balanced address and command
datapath (setup and hold margin) it's recommended to change the phase of the clk given by the pll used by the ddr controller. I have read that in the app_note www.altera.com/literature/hb/external-memory/emi_tut_ddr.pdf
