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Altera_Forum
Honored Contributor
Honored ContributorDDR Data window
Hi everybody, When I try to change to 55º the pll clk phase wich affects the ddr address&command signals, the following message appears: Critical Warning: PLL clock must be phase shifted ...
Altera_ForumHonored Contributor
Honored ContributorI suggest trusting the controller created PLL and don't change the settings. If the hardware is OK, it works fine.
