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Honored Contributor
Honored ContributorDDR Data window
Hi everybody, When I try to change to 55º the pll clk phase wich affects the ddr address&command signals, the following message appears: Critical Warning: PLL clock must be phase shifted ...
Altera_ForumHonored Contributor
Honored ContributorYou don't need to change any PLL options that are set by HPMC2. The controller creates required clock according to Your memory chip settings and gives differential clock output. You don't need any other PLL to be instantiated.
