DDIO Input nodes could not be constrained by the Fitter to improve DDIO timing

This is typically the best approach even with the high-end FPGA families. DDR interfaces have special pin requirements.

This is how I usually approach it:

1 - Constrain the interface to an edge of the chip.

2 - Let the Fitter decide which pins to use (because it knows the rules).

3 - back-annotate

4 - Make tweaks as needed

5 - Re-compile to ensure the fitter agrees with your tweaks.

6 - repeat steps 4&5 as needed.