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Altera_Forum
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16 years ago

DDIO Input nodes could not be constrained by the Fitter to improve DDIO timing

Hello, I have a design with a 16-bit wide DDR2 memory and a 10 bit DDR interface to another peripheral, that makes a total of 26 DDR Input pins. I get this Info+Warning during the fitting...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi all, I found a "solution":

- remove from the QSF all the DDR IOs in the problematic bank

- place and route the design, let quartus place those IOs

- backannotate the IOs if there are no DDIO warnings

If this problem occurs when the board is already layed out you are in trouble, I'm not sure what caused that tbh, maybe just a limitation of the Cyclone 3 cheap and cheerful family with not a lot reources in the periphery...

regards,

-Ulises