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Altera_Forum's avatar
Altera_Forum
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16 years ago

DDIO Input nodes could not be constrained by the Fitter to improve DDIO timing

Hello,

I have a design with a 16-bit wide DDR2 memory and a 10 bit DDR interface to another peripheral, that makes a total of 26 DDR Input pins.

I get this Info+Warning during the fitting process:

info: following ddio input nodes could not be constrained by the fitter to improve ddio timing. info: ddio capture registers for pin "rxd_2[0]" could not be constrained to the chip periphery. warning: ddio node "altddio_in:phy2_iob_ddr_in|ddio_in_5uf:auto_generated|input_cell_h[0]" could not be constrained to the chip periphery at lab_x1_y10_n0 because there are not enough available control signals in this lab for ddio register placement.

It happens for 3 Input signals, not for the other 23, the set-up time for the failing IOs is really bad compared to the peripheral DDIO FFs. I'm using a Cyclone III and Quartus II 9.1. We are still laying out the board and can change the IO allocation but would like to know why the fitter is not capable of placing those FFs in the IOs.

Has anyone had this problem in the past?

Thanks in advace,

-Ulises

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi all, I found a "solution":

    - remove from the QSF all the DDR IOs in the problematic bank

    - place and route the design, let quartus place those IOs

    - backannotate the IOs if there are no DDIO warnings

    If this problem occurs when the board is already layed out you are in trouble, I'm not sure what caused that tbh, maybe just a limitation of the Cyclone 3 cheap and cheerful family with not a lot reources in the periphery...

    regards,

    -Ulises
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    This is typically the best approach even with the high-end FPGA families. DDR interfaces have special pin requirements.

    This is how I usually approach it:

    1 - Constrain the interface to an edge of the chip.

    2 - Let the Fitter decide which pins to use (because it knows the rules).

    3 - back-annotate

    4 - Make tweaks as needed

    5 - Re-compile to ensure the fitter agrees with your tweaks.

    6 - repeat steps 4&5 as needed.