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Altera_Forum
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16 years ago

DCLK after config in PS mode

We're doing a design where we're planning on configuring a EP3C5 using passive serial from a micro controller.

We're limited by the number of interconnects and I was wondering about the possibility of connecting a processor GPIO pin to both the DCLK line and a user I/O line on the FPGA.

As long as we wait until after configuration, is there any issue with the DCLK line toggling high and low?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    There is no problem. In fact the DCLK can be used as a regular I/O on the FPGA after configuration, so you don't need to connect it to an extra I/O.

    Have a look in Quartus in the device settings, click on the 'Device and pins options...' button, and select the 'dual purpose pins' tab.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    There is no problem. In fact the DCLK can be used as a regular I/O on the FPGA after configuration, so you don't need to connect it to an extra I/O.

    Have a look in Quartus in the device settings, click on the 'Device and pins options...' button, and select the 'dual purpose pins' tab.

    --- Quote End ---

    DCLK is a dual purpose pin in active serial configuration. But if you switch the settings to passive serial, the DCLK pin disappears from the dual purpose pin list.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Oh yes, it seems that only the DATA[0] can be used as a dual purpose pin in the PS configuration.

    If you have a look at the cyclone iii configuration (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf) in the handbook, page 9-37, you can see that the Cyclone III on the left continues to see it's DCLK toggling after it has been configured, when the one on the right is receiving its own configuration. So I would guess that it would be ok. It would need to be tested to be sure it's not a problem, though.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Here is my design we're going to layout with:

    http://i1008.photobucket.com/albums/af207/matthew_db/work/config.jpg?t=1255448620

    The 6 net tagged lines going in or out of the 74LV365 are going to GPIO pins over a short ribbon cable.

    I can use the AT17LV010 during development and as a backup plan. For early production the AT17LV010, the socket and the header would be no place. If this works, they can go at a later version of the board.

    I went ahead and included both DATA[0] and DCLK since there are extra gates on a hex tri-state buffer.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Oh yes, it seems that only the DATA[0] can be used as a dual purpose pin in the PS configuration.

    If you have a look at the Cyclone III configuration in the handbook, page 9-37, you can see that the Cyclone III on the left continues to see it's DCLK toggling after it has been configured, when the one on the right is receiving its own configuration. So I would guess that it would be ok. It would need to be tested to be sure it's not a problem, though.

    --- Quote End ---

    I have just tested this and dclk is usable as a io pin in passive serial. You need to set e.g. active serial mode to synthesize this, but the resulting file can be uploaded via passive serial and afterwards both dclk and data[0] defintitely work as user pins.