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Altera_Forum
Honored Contributor
Honored Contributordcfifo timing details
I am trying to find out some timing info of dcfifo, but couldn't find it anywhere. The "Single- and Dual-Clock FIFO Megafunction User Guide" talks about the flag latency, but failed to disclose which ports are flopped-in or flopped-out. For example, one would think that rdempty is flopped using rdclk, but it is NOT (my design couldn't meet timing unless I explicitly flop rdempty)!
Also why would rdusedw[] have 2-rdclk latency from rdreq (Table 3 on pp.8 of the user guide)? This signal is generated in the rdclk domain and thus should have 1-rdclk latency from rdreq. This extra cycle latency really complicates my design. Is it possible to tweak the megacore somehow?11 Replies
Altera_Forumthe Rdusedw has to have a 2 clock latency in a DC fifo because it has to get the difference in the read and write counters that are in 2 difference clock domains, and needs to synchronise them - hence the extra clock.
As for timing problems with rdempty - what are you doing with this signal? doing some logic with it?
