Data corrupted, any problem with VHDL codes

HI everyone.

I just have a quick question to ask.

When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following piece of code, the code "content(i) <= content(i+1)" is repeated 65 times (content is an array of 8bit number), and the data I get at the output of the Modules (dataout[7:0]) is corrupted at some points:

-- ram.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity RAM is

generic ( bits: integer := 8;

words: integer:= 66);

port (clk_in: in std_logic;

clk_out: in std_logic;

we: in std_logic;

re: in std_logic;

reset: in std_logic;

datain: in std_logic_vector(bits - 1 downto 0);

dataout: out std_logic_vector(bits - 1 downto 0)

);

end RAM;

architecture beh of RAM is

signal readp: integer range 0 to words;

type table is array (0 to words - 1) of std_logic_vector(bits-1 downto 0);

signal content: table :=(others => "10000000");

begin

process(reset,clk_in, we)

begin

if (reset = '1') then

content <= (others => "10000000");

elsif (clk_in'event and clk_in = '1') then

if (we = '1') then

for i in 0 to words - 2 loop

content(i) <= content(i+1); --***could it be this line? ***

end loop;

content(words - 1) <= datain;

end if;

end if;

end process;

process(clk_out, re)

begin

if (clk_out'event and clk_out = '1') then

if(re = '1') then

dataout <= content(readp);

end if;

end if;

end process;

process(clk_out, re, reset)

begin

if (reset = '1') then

readp <= 0;

elsif (clk_out'event and clk_out = '0') then

if(re = '1') then

readp <= readp + 1;

if(readp = words - 1) then

readp <= 0;

end if;

end if;

end if;

end process;

end beh;

Any suggestion would be greatlly appreciated.

Cheers.

J.