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Altera_Forum's avatar
Altera_Forum
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17 years ago

Data corrupted, any problem with VHDL codes

HI everyone. I just have a quick question to ask. When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following pie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You seem to infer a dual clock shift register. You better instantiate an altera dual clock ram.

Your loop is not the problem but it could be your use of two clocks going wrong.