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Altera_Forum's avatar
Altera_Forum
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17 years ago

Data corrupted, any problem with VHDL codes

HI everyone. I just have a quick question to ask. When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following pie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I don't see clearly, why you organized the code this way. However, when you write data to the shift register, the content of the complete array is shifted, and can't be accessed consistently for a time interval of several ns. If clock_out is unrelated to clock_in, you have no gurantee to read consistent data. To my opinion, the issue can't be avoided with the present structure.