Data corrupted, any problem with VHDL codes

You can't do this if those are two independent clocks; you will most likely need to either look up how to infer dual port memory from your manufacturer or simply use their dual port ram blocks. If the two clocks are real you really should just put this in one clocked process. Again it's always good to refer to your manufacturers manuals on how to infer RAM. You'll find it's very similar to the way you set up "table" but very unlike your read and write processes. You can read and write with two separate clocks but it will require handshake signals using clock domain synchronization flip flops. It will not be single clock cycle access either.