DAC5672 Sine output

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Here's how i am changing values in VHDL

ADJUSTING_OFFSET: PROCESS(sys_clk, sin_out_reg)

BEGIN

IF reset_n = '0' THEN

sin_out_adj <= (others=>'0');

ELSIF rising_edge(sys_clk) THEN

IF nco_sin_out(13) = '1' THEN

sin_out_adj <= NOT(nco_sin_out)+"00000000000001";

ELSE

sin_out_adj<= '1'& nco_sin_out(12 downto 0);

END IF;

END IF;

-- END IF;

END PROCESS;

But i am not getting a clean sine wave out ?? the frequency of generated signal is correct

see image attached

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To change 2's complement to offset binary just invert the sign bit.

sign_inv = not data(13);

data <= sign_inv & data(12 downto 0);

keep this combinatorial to avoid latency problems