Altera_Forum
Honored Contributor
17 years agoDAC Converter
Hi,
I try to make a DA conversion with this board: http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html But I am not able to make something which works well. When I check my output to an oscillo, nothing happens...:confused: This is my VHDL code:entity conv_DA is
port(
clk2:in std_logic;
output: out std_logic_vector(13 downto 0));
end entity conv_DA;
architecture behavior2 of conv_DA is
signal data: std_logic_vector(13 downto 0):="00000000000000"; --data 14 bits on the chip
Begin
Process (clk2)
Begin
if clk2='0' and (clk2'event) then data<=data+'1'; --incrementation
end if;
-- wait for 35 ns;
end process;
Process (data)
Begin
output<=data; --update of the output
End Process;
end architecture behavior2; This is the VHDL source for the clock: ( I use the 100MHz clock of the board and I slow it with this code) entity defclk is
port(clk : in std_logic;
clk2 : out std_logic);
end entity defclk;
architecture behavior of defclk is
signal compteur: std_logic_vector(26 downto 0):="000000000000000000000000000" ;
begin
Process(clk)
Begin
if clk='0' and (clk'event) then compteur<=compteur+1;
end if;
end process;
clk2<= compteur(26); -- 10ns => about 1s
end architecture behavior; I think my pins are right. I have put the jumper on the pin 5&6 on J19 for enable the clock. If someone could help me, or could give a code which works :rolleyes: Thanks!