[D-TYPE flip-flop vhdl] a brief question about process

Hello guys,

here is vhdl code from the lecture slide. I don't understand why the prof chose the put the output outside of the process. Just wondering, if the clock is slow, and it's not yet at falling yet, then process is not triggered. And Qtemp will have no value assign to it. What will happen to Q ?

LIBRARY IEEE ;

USE IEEE . STD_LOGIC_1164 . ALL ;

---------------------------------------------

ENTITY Negative_Edge_D_FlipFlop_with_Asynchronous_RS IS

PORT (

D , Set , Reset : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;

Q , Qbar : OUT STD_LOGIC

) ;

END ;

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ARCHITECTURE behavioural OF Negative_Edge_D_FlipFlop_with_Asynchronous_RS IS

SIGNAL Qtemp : STD_LOGIC ;

BEGIN

PROCESS ( Clock , Set , Reset )

BEGIN

-- note syntax for stating ‘Q’ becomes ‘D’ on falling edge of input clock

-- there is a ‘rising_edge’ notation also if you want positive edge triggering

IF ( Reset = '0' ) THEN

Qtemp <= '0' ;

ELSIF ( Set = '0‘ ) THEN

Qtemp <= '1' ;

ELSIF ( falling_edge ( Clock ) ) THEN

Qtemp <= D ;

END IF ;

END PROCESS ;

Q <= Qtemp ;

QBar <= NOT Qtemp ;