Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

D flip-flop latches FPGA input pin's signal wrong!

Hello everyone: Why D flip-flop latches signal which comes from the FPGA input pin will go wrong and how to avoid it? when deal with the externally input RGB signal deriving form a LCD driver, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

your signal In_LCD_DE is from different clock domain (i.e.not synchronised to this clock) and so correctly you have use two stage synchroniser. You must expect this behavior and do not sample until second flip. So in principle don't worry about signaltap result. However you got a problem reported so I assume some other clocks are involved and we need better picture of your design.